Double Switching Pwms; Adc Triggering - NXP Semiconductors freescale KV4 Series Reference Manual

37.5.1.4 Double Switching PWMs

Double switching PWM output is supported to aid in single shunt current measurement
and three phase reconstruction. This method support two independent rising edges and
two independent falling edges per PWM cycle. The VAL2 and VAL3 registers are used
to generate the even channel (labelled as PWM_A in the figure) while VAL4 and VAL5
are used to generate the odd channel. The two channels are combined using XOR logic
(force out logic) as the following figure shows. The DBLPWM signal can be run through
the deadtime insertion logic.
VAL1 ($0100)
VAL3
VAL5
VAL0 ($0000)
VAL4
VAL2
INIT ($FF00)
PWM_A
PWM_B
DBLPWM
Figure 37-228. Double Switching Output Example

37.5.1.5 ADC Triggering

In cases where the timing of the ADC triggering is critical, it must be scheduled as a
hardware event instead of software activated. With this PWM module, multiple ADC
triggers can be generated in hardware per PWM cycle without the requirement of another
timer module. Figure 37-229
Freescale Semiconductor, Inc.
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)
shows how this is accomplished. When specifying
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
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