Intermediate Load - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Table 39-254. FTM behavior when the chip Is in BDM mode (continued)

CH(n)F Bit FTM Channels Output

can be set Functional mode

Note that if BDMMODE[1:0] = 2'b00 then the channels outputs remain at the value

when the chip enters in BDM mode, because the FTM counter is stopped. However, the

following situations modify the channels outputs in this BDM mode.

• Write any value to CNT register; see

updated with the CNTIN register value and the channels outputs are updated to the

initial value – except for those channels set to Output Compare mode.

• FTM counter is reset by PWM Synchronization mode; see

synchronization. In this case, the FTM counter is updated with the CNTIN register

value and the channels outputs are updated to the initial value – except for channels

in Output Compare mode.

• In the channels outputs initialization, the channel (n) output is forced to the CH(n)OI

bit value when the value 1 is written to INIT bit. See Initialization.

The BDMMODE[1:0] = 2'b00 must not be used with the

control. Even if the fault control is enabled and a fault condition

exists, the channels outputs values are updated as above.

If CLKS[1:0] = 2'b00 in BDM, a non-zero value is written to

CLKS in BDM, and CnV = CNTIN when the BDM is disabled,

then the CHnF bit is set (since if the channel is a 0% EPWM

signal) when the BDM is disabled.

39.5.27 Intermediate load

The PWMLOAD register allows to update the MOD, CNTIN, and C(n)V registers with

the content of the register buffer at a defined load point. In this case, it is not required to

use the PWM synchronization.

There are multiple possible loading points for intermediate load:

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 39 FlexTimer Module (FTM)

Writes to MOD, CNTIN, and C(n)V Registers

Functional mode

reset. In this case, the FTM counter is