Interrupts And Dma Requests - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA)
26.6 Resets
The XBAR module can be reset by only a hard reset, which forces all registers to their
reset state.
26.7 Clocks
All sequential functionality is controlled by the Bus Clock.

26.8 Interrupts and DMA Requests

For each XBAR_OUT[*] output with XBAR_CTRL register support, DMA or interrupt
functionality can be enabled by setting the corresponding XBAR_CTRL register bit
DENn or IENn to 1. DENn and IENn should not be set to 1 at the same time for the same
output XBAR_OUT[n].
Setting DENn to 1 enables DMA functionality for XBAR_OUT[n]. When DMA
functionality is enabled, the output DMA_REQ[n] reflects the value of STSn. Thus the
DMA request asserts when the edge specified by EDGEn is detected on XBAR_OUT[n].
Also, a rising edge on DMA_ACK[n] sets STSn to zero and thus clears the DMA request.
When DEN is 0, DMA_REQ[n] is held low and DMA_ACK[n] is ignored.
Setting IENn to 1 enables interrupt functionality for XBAR_OUT[n]. When interrupt
functionality is enabled, the output INT_REQ[n] reflects the value of STSn. Thus the
interrupt request asserts when the edge specified by EDGEDENn is detected on
XBAR_OUT[n]. The interrupt request is cleared by writing a 1 to STSn. When IENn is 0,
INT_REQ[n] is held low.
DENn and IENn should not be set to 1 at the same time for the same output
XBAR_OUT[n].
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc. 511