Functional Description - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description

Field
Setting these bits removes the combinational path and uses the filterred and latched fault signals as the
fault source to disable the PWM outputs. This eliminates fault glitches from creating PWM output glitches
but also increases the latency to respond to a real fault.
0 There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
with the filtered and latched fault signals to disable the PWM outputs.
1 The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and
latched fault signals are used to disable the PWM outputs.
37.5 Functional Description
37.5.1 PWM Capabilities
This section describes some capabilities of the PWM module.
37.5.1.1 Center Aligned PWMs
Each submodule has its own timer that is capable of generating PWM signals on two
output pins. The edges of each of these signals are controlled independently as shown in
Figure 37-224.
826
PWMA_FCTRL2 field descriptions (continued)
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Description
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