One-Shot Capture Mode - NXP Semiconductors freescale KV4 Series Reference Manual

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The ELS(n)B:ELS(n)A bits select the edge that is captured by channel (n), and ELS(n

+1)B:ELS(n+1)A bits select the edge that is captured by channel (n+1). If both

ELS(n)B:ELS(n)A and ELS(n+1)B:ELS(n+1)A bits select the same edge, then it is the

period measurement. If these bits select different edges, then it is a pulse width

measurement.

In the Dual Edge Capture mode, only channel (n) input is used and channel (n+1) input is

If the selected edge by channel (n) bits is detected at channel (n) input, then CH(n)F bit is

set and the channel (n) interrupt is generated (if CH(n)IE = 1). If the selected edge by

channel (n+1) bits is detected at channel (n) input and (CH(n)F = 1), then CH(n+1)F bit is

set and the channel (n+1) interrupt is generated (if CH(n+1)IE = 1).

The C(n)V register stores the value of FTM counter when the selected edge by channel

(n) is detected at channel (n) input. The C(n+1)V register stores the value of FTM

counter when the selected edge by channel (n+1) is detected at channel (n) input.

In this mode, a coherency mechanism ensures coherent data when the C(n)V and C(n

+1)V registers are read. The only requirement is that C(n)V must be read before C(n

• The CH(n)F, CH(n)IE, MS(n)A, ELS(n)B, and ELS(n)A

bits are channel (n) bits.

• The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and

ELS(n+1)A bits are channel (n+1) bits.

• The Dual Edge Capture mode must be used with

ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A =

0:1 or 1:0 and the FTM counter in

39.5.24.1 One-Shot Capture mode

The One-Shot Capture mode is selected when (DECAPEN = 1), and (MS(n)A = 0). In

this capture mode, only one pair of edges at the channel (n) input is captured. The

ELS(n)B:ELS(n)A bits select the first edge to be captured, and ELS(n+1)B:ELS(n+1)A

bits select the second edge to be captured.

The edge captures are enabled while DECAP bit is set. For each new measurement in

One-Shot Capture mode, first the CH(n)F and CH(n+1) bits must be cleared, and then the

DECAP bit must be set.

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 39 FlexTimer Module (FTM)

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