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Functional Description
41.4.19 Upper Position Compare Register (ENC_UCOMP)
Address: 4005_5000h base + 24h offset = 4005_5024h
Bit
15
14
13
Read
Write
Reset
1
1
1
Field
COMP[31:16]
This read/write register contains the upper (most significant) half of the position compare register. When
the value of POS matches the value of COMP, the CTRL[CMPIRQ] flag is set and the POSMATCH output
is asserted.
41.4.20 Lower Position Compare Register (ENC_LCOMP)
Address: 4005_5000h base + 26h offset = 4005_5026h
Bit
15
14
13
Read
Write
Reset
1
1
1
Field
COMP[15:0]
This read/write register contains the lower (least significant) half of the position compare register. When
the value of POS matches the value of COMP, the CTRL[CMPIRQ] flag is set and the POSMATCH output
is asserted.
41.5 Functional Description
The following timing diagram shows the basic operation of a quadrature incremental
position quadrature decoder.
PHASEA
PHASEB
COUNT
UP/DN
1060
12
11
10
9
COMP[31:16]
1
1
1
1
ENC_UCOMP field descriptions
12
11
10
9
COMP[15:0]
1
1
1
1
ENC_LCOMP field descriptions
+1 +1 +1 +1 +1 +1 +1
Figure 41-23. Quadrature Decoder Signals
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
8
7
6
5
1
1
1
1
Description
8
7
6
5
1
1
1
1
Description
–1 –1 –1 –1 –1 –1 –1 –1
+1
4
3
2
1
1
1
1
1
4
3
2
1
1
1
1
1
Freescale Semiconductor, Inc.
0
1
0
1
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