Software Output Control - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
Note that the ELSnB:ELSnA bits value should be considered because they define the
active state of the channels outputs. In Low-True (ELSnB:ELSnA = X:1) Combine mode,
the channel (n) output is forced high at the beginning of the period, forced low at the
channel (n) match and forced high at the channel (n+1) match. When inverting is
selected, the channels (n) and (n+1) present waveforms as shown in the following figure.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
before the inverting
channel (n+1) output
before the inverting
write 1 to INV(m) bit
INV(m) bit buffer
INVCTRL register
synchronization
INV(m) bit
channel (n) output
after the inverting
channel (n+1) output
after the inverting
NOTE
INV(m) bit selects the inverting to the pair channels (n) and (n+1).
Figure 39-228. Channels (n) and (n+1) outputs after the inverting in Low-True
The inverting feature is not available in Output Compare mode.

39.5.13 Software output control

The software output control forces the channel output according to software defined
values at a specific time in the PWM generation.
The software output control is selected when:
• QUADEN = 0
• DECAPEN = 0, and
• CHnOC = 1
990
(ELSnB:ELSnA = X:1) Combine mode
Note
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.