Lptmr Signal Descriptions; Detailed Signal Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

42.3 LPTMR signal descriptions

Signal
LPTMR_ALTn

42.3.1 Detailed signal descriptions

Table 42-3. LPTMR interface—detailed signal descriptions
Signal
LPTMR_ALTn
42.4 Memory map and register definition
Absolute
address
(hex)
4004_0000 Low Power Timer Control Status Register (LPTMR_CSR)
Freescale Semiconductor, Inc.
Table 42-1. Modes of operation (continued)
Modes
The LPTMR continues to operate normally and
Low-Leakage may be configured to exit the low-power mode
by generating an interrupt request.
The LPTMR operates normally in Pulse Counter
Debug mode, but counter does not increment in Time
Counter mode.
Table 42-2. LPTMR signal descriptions
I/O Description
I Pulse Counter Input pin
I/O
I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning
Timing
LPTMR memory map
Register name
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 42 Low-Power Timer (LPTMR)
Description
Description
Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
Width
Access
(in bits)
32 R/W
Section/
Reset value
page
0000_0000h 42.4.1/1066
1065