Memory Map/Register Definition; Tcd Memory; Tcd Initialization - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

In Normal mode, the eDMA transfers data between a source and a destination. The source and

destination can be a memory block or an I/O block capable of operation with the eDMA.

A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the

transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that

transfers these NBYTES per service request. Each service request executes one iteration of the

major loop, which transfers NBYTES of data.

DMA operation is configurable in Debug mode via the control register:

Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer

completes, the device enters Wait mode.

23.3 Memory map/register definition

The eDMA's programming model is partitioned into two regions:

• The first region defines a number of registers providing control functions

• The second region corresponds to the local transfer control descriptor (TCD)

Each channel requires a 32-byte transfer control descriptor for defining the desired data

movement operation. The channel descriptors are stored in the local memory in

sequential order: channel 0, channel 1, ... channel 15. Each TCDn definition is presented

as 11 registers of 16 or 32 bits.

Prior to activating a channel, you must initialize its TCD with the appropriate transfer

Freescale Semiconductor, Inc.

Table 23-3. Modes of operation

• If CR[EDBG] is cleared, the DMA continues to operate.

• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a

channel is active, the eDMA continues operation until the channel retires.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 23 Direct Memory Access Controller (eDMA)