Modes Of Operation; External Signal Description - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Modes of operation

• For bank 0: Read accesses to consecutive 32-bit spaces in memory return the

second, third, and fourth read data with no wait states. The memory returns 128

bits via the 32-bit bus access.

• Crossbar master access protection for setting no access, read-only access, write-

only access, or read/write access for each crossbar master.

• For bank 0: Acceleration of data transfer from program flash memory to the device:

• 128-bit prefetch speculation buffer with controls for instruction/data access per

• 4-way, 2-set, 128-bit line size cache for a total of eight 128-bit entries with

controls for replacement algorithm and lock per way

• Single-entry buffer

• Invalidation control for the speculation buffer and the single-entry buffer

31.2 Modes of operation

The FMC only operates when a bus master accesses the flash memory.

For any device power mode where the flash memory cannot be accessed, the FMC is

The FMC has no external signals.

31.4 Memory map and register descriptions

The programming model consists of the FMC control registers and the program visible

cache (data and tag/valid entries).

Program the registers only while the flash controller is idle (for

example, execute from RAM). Changing configuration settings

while a flash access is in progress can lead to non-deterministic

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.