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Initialization/application information
• External Stop mode
• Module Disable mode – Clock gating of non-memory mapped logic
44.5.8.1 Stop mode (External Stop mode)
This module supports the Stop mode protocol. When a request is made to enter External
Stop mode, the module acknowledges the request . If a serial transfer is in progress, then
this module waits until it reaches the frame boundary before it is ready to have its clocks
shut off . While the clocks are shut off, this module's memory-mapped logic is not
accessible. This also puts the module in STOPPED state. The SR[TXRXS] bit is cleared
to indicate STOPPED state. The states of the interrupt and DMA request signals cannot
be changed while in External Stop mode.
44.5.8.2 Module Disable mode
Module Disable mode is a block-specific mode that the module can enter to save power.
Host CPU can initiate the Module Disable mode by setting the MDIS bit in the MCR.
The Module Disable mode can also be initiated by hardware.
When the MDIS bit is set, the module negates the Clock Enable signal at the next frame
boundary. Once the Clock Enable signal is negated, it is said to have entered Module
Disable Mode. This also puts the module in STOPPED state. The SR[TXRXS] bit is
cleared to indicate STOPPED state.If implemented, the Clock Enable signal can stop the
clock to the non-memory mapped logic. When Clock Enable is negated, the module is in
a dormant state, but the memory mapped registers are still accessible. Certain read or
write operations have a different effect when the module is in the Module Disable mode.
Reading the RX FIFO Pop Register does not change the state of the RX FIFO. Similarly,
writing to the PUSHR Register does not change the state of the TX FIFO or CMD FIFO.
Clearing either of the FIFOs has no effect in the Module Disable mode. Changes to the
DIS_TXF and DIS_RXF fields of the MCR have no effect in the Module Disable mode.
In the Module Disable mode, all status bits and register flags in the module return the
correct values when read, but writing to them has no effect. Writing to the TCR during
Module Disable mode has no effect. Interrupt and DMA request signals cannot be cleared
while in the Module Disable mode.
44.6 Initialization/application information
This section describes how to initialize the module.
1224
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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