Enabling The Tap Controller - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
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0
The value shown adjacent to each state transition in this figure represents the value of TMS at the time
of a rising edge of TCK.
Figure 48-4. IEEE 1149.1-2001 TAP controller finite state machine

48.4.3.1 Enabling the TAP controller

The JTAGC TAP controller is enabled by setting the JTAGC enable to a logic 1 value.
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TEST LOGIC
RESET
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1
SELECT -DR-SCAN
RUN-TEST/IDLE
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CAPTURE-DR
0
1
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
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1
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SHIFT -DR
0
1
1
EXIT1-DR
0
P AUSE-DR
0
1
0
EXIT2-DR
1
UPDA TE-DR
0
1
SELECT-IR-SCAN
0
CAPTURE-IR
0
SHIFT -IR
0
1
1
EXIT1-IR
0
P AUSE-IR
0
1
EXIT2-IR
1
UPDA TE-IR
1
0
Freescale Semiconductor, Inc.