Peripheral Doze - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Clocking Modes

GPIO registers via the IOPORT is supported, the GPIO port data input registers do not

return valid data since clocks are disabled to the Port Control and Interrupt modules. By

writing to the GPIO port data output registers, it is possible to control those GPIO ports

that are configured as output pins.

Compute Operation is controlled by the CPO register in the MCM, which is only

accessible to the CPU. Setting or clearing the CPOREQ bit in the MCM initiates entry or

exit into Compute Operation. Compute Operation can also be configured to exit

automatically on detection of an interrupt, which is required in order to service most

interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and

any edge sensitive interrupts can be serviced without exiting Compute Operation.

When entering Compute Operation, the CPOACK status bit indicates when entry has

completed. When exiting Compute Operation in Run mode, the CPOACK status bit

negates immediately. When exiting Compute Operation in VLP Run mode, the exit is

delayed to allow the PMC to handle the change in power consumption. This delay means

the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed

without generating a bus error.

The DMA wakeup is also supported during Compute Operation and causes the CPOACK

status bit to clear and the AIPS peripheral space to be accessible for the duration of the

DMA wakeup. At the completion of the DMA wakeup, the device transitions back into

Compute Operation.

7.2.4 Peripheral Doze

Several peripherals support a peripheral Doze mode, where a register bit can be used to

disable the peripheral for the duration of a low power mode. The Flash can also be placed

in a low power state during Peripheral Doze via a register bit in the SIM.

Peripheral Doze is defined to include all of the modes of operation listed below.

• The CPU is in wait mode.

• The CPU is in stop mode, including the entry sequence and for the duration of a

• The CPU is in Compute Operation, including the entry sequence and for the duration

of a DMA wakeup.

Peripheral Doze can therefore be used to disable selected bus masters or slaves for the

duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves

immediately on entry into any stop mode (or Compute Operation), instead of waiting for

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.