Block Diagram - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
Some applications require regular software updates for proper
operation. Failure to provide regular software updates could
result in destroying the hardware setup.
To accommodate this situation, PWM outputs are placed in their inactive states in stop
mode, and they can optionally be placed in inactive states in wait and debug (EOnCE)
modes. PWM outputs are reactivated (assuming they were active beforehand) when these
modes are exited.
Table 37-1. Modes when PWM Operation is Restricted
Mode Description
Stop PWM outputs are inactive.
Wait PWM outputs are driven or inactive as a function of CTRL2[WAITEN].
CPU and peripheral clocks continue to run, but the CPU may stall for periods of time. PWM outputs
Debug
are driven or inactive as a function of CTRL2[DBGEN].

37.2.3 Block Diagram

The following figure is a block diagram of the PWM.
768
CAUTION
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.