Chapter 7 Power Management; Clocking Modes; Partial Stop - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 7
Power Management
7.1 Introduction
This chapter describes the various chip power modes and functionality of the individual
modules in these modes.

7.2 Clocking Modes

This section describes the various clocking modes supported on this device.

7.2.1 Partial Stop

Partial Stop is a clocking option that can be taken instead of entering Stop mode and is
configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is
only partially entered, which leaves some additional functionality alive at the expense of
higher power consumption. Partial Stop can be entered from either Run mode or VLP
Run mode.
When configured for PSTOP2, only the core and system clocks are gated and the bus
clock remains active. The bus masters and bus slaves clocked by the system clock enter
Stop mode, but the bus slaves clocked by the bus clock remain in Run (or VLP Run)
mode. The clock generators in the MCG and the on-chip regulator in the PMC also
remain in Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an
asynchronous interrupt from a bus master or bus slave clocked by the system clock, or a
synchronous interrupt from a bus slave clocked by the bus clock. If configured, a DMA
request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for
the duration of a DMA transfer before the device is transitioned back into PSTOP2.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc. 105