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Memory map/register definition
19.4 Memory map/register definition
The LLWU includes the following registers:
• Wake-up source enable registers
• Enable external pin input sources
• Enable internal peripheral interrupt sources
• Wake-up flag registers
• Indication of wakeup source that caused exit from a low-leakage power mode
includes external pin or internal module interrupt
• Wake-up pin filter enable registers
The LLWU registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
All LLWU registers are reset by Chip Reset not VLLS and by
reset types that trigger Chip Reset not VLLS. Each register's
displayed reset value represents this subset of reset types.
LLWU registers are unaffected by reset types that do not trigger
Chip Reset not VLLS. For more information about the types of
reset on this chip, refer to the
Absolute
address
(hex)
4007_C000 LLWU Pin Enable 1 register (LLWU_PE1)
4007_C001 LLWU Pin Enable 2 register (LLWU_PE2)
4007_C002 LLWU Pin Enable 3 register (LLWU_PE3)
4007_C003 LLWU Pin Enable 4 register (LLWU_PE4)
4007_C004 LLWU Pin Enable 5 register (LLWU_PE5)
4007_C005 LLWU Pin Enable 6 register (LLWU_PE6)
4007_C006 LLWU Pin Enable 7 register (LLWU_PE7)
4007_C007 LLWU Pin Enable 8 register (LLWU_PE8)
4007_C008 LLWU Module Enable register (LLWU_ME)
4007_C009 LLWU Pin Flag 1 register (LLWU_PF1)
4007_C00A LLWU Pin Flag 2 register (LLWU_PF2)
4007_C00B LLWU Pin Flag 3 register (LLWU_PF3)
306
NOTE
Introduction
LLWU memory map
Register name
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
details.
Width
Access
Reset value
(in bits)
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
8
R/W
00h
Freescale Semiconductor, Inc.
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page
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