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Functional description
Each one of the message buffers can be an interrupt source, if its corresponding IMASK
bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer,
under the assumption that the buffer is initialized for either transmission or reception.
Each of the buffers has an assigned flag bit in the CAN_IFLAG registers. The bit is set
when the corresponding buffer completes a successful transfer and is cleared when the
CPU writes it to 1 (unless another interrupt is generated at the same time).
It must be guaranteed that the CPU clears only the bit causing
the current interrupt. For this reason, bit manipulation
instructions (BSET) must not be used to clear interrupt flags.
These instructions may cause accidental clearing of interrupt
flags which are set after entering the current interrupt service
routine.
If the Rx FIFO is enabled (CAN_MCR[RFEN] = 1) and DMA is disabled
(CAN_MCR[DMA] = 0), the interrupts corresponding to MBs 0 to 7 have different
meanings. Bit 7 of the CAN_IFLAG1 register becomes the "FIFO Overflow" flag; bit 6
becomes the "FIFO Warning" flag, bit 5 becomes the "Frames Available in FIFO" flag
and bits 4-0 are unused. See the description of the Interrupt Flags 1 Register
(CAN_IFLAG1) for more information.
If both Rx FIFO and DMA are enabled (CAN_MCR[RFEN] and CAN_MCR[DMA] = 1)
the FlexCAN does not generate any FIFO interrupt. The bit 5 of the CAN_IFLAG1
register still indicates "Frames Available in FIFO" and generates a DMA request. The
bits 7, 6, 4-0 are unused.
For a combined interrupt where multiple MB interrupt sources are OR'd together, the
interrupt is generated when any of the associated MBs (or FIFO, if applicable) generates
an interrupt. In this case, the CPU must read the CAN_IFLAG registers to determine
which MB or FIFO source caused the interrupt.
The interrupt sources for Bus Off, Bus Off Done, Error, Wake Up, Tx Warning and Rx
Warning generate interrupts like the MB interrupt sources, and can be read from
CAN_ESR1 register. The Bus Off, Error, Tx Warning, and Rx Warning interrupt mask
bits are located in the CAN_CTRL1 Register; the Wake-Up interrupt mask bit is located
in the CAN_MCR.
43.5.12 Bus interface
The CPU access to FlexCAN registers are subject to the following rules:
1164
Note
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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