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Functional description
The clock frequency mentioned in the preceding tables is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
44.5.4 Transfer formats
The SPI serial communication is controlled by the Serial Communications Clock (SCK)
signal and the PCS signals. The SCK signal provided by the master device synchronizes
shifting and sampling of the data on the SIN and SOUT pins. The PCS signals serve as
enable signals for the slave devices.
In Master mode, the CPOL and CPHA bits in the Clock and Transfer Attributes Registers
(CTARn) select the polarity and phase of the serial clock, SCK.
• CPOL - Selects the idle state polarity of the SCK
• CPHA - Selects if the data on SOUT is valid before or on the first SCK edge
Even though the bus slave does not control the SCK signal, in Slave mode the values of
CPOL and CPHA must be identical to the master device settings to ensure proper
transmission. In SPI Slave mode, only CTAR0 is used.
The module supports four different transfer formats:
• Classic SPI with CPHA=0
• Classic SPI with CPHA=1
• Modified Transfer Format with CPHA = 0
• Modified Transfer Format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with
peripherals that require longer setup times. The module can sample the incoming data
later than halfway through the cycle to give the peripheral more setup time. The MTFE
bit in the MCR selects between Classic SPI Format and Modified Transfer Format.
In the interface configurations, the module provides the option of keeping the PCS
signals asserted between frames. See
1210
NOTE
Continuous Selection Format
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
for details.
Freescale Semiconductor, Inc.
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