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48.1.3.2 IEEE 1149.1-2001 defined test modes
The JTAGC block supports several IEEE 1149.1-2001 defined test modes. A test mode is
selected by loading the appropriate instruction into the instruction register while the
JTAGC is enabled. Supported test instructions include EXTEST, HIGHZ, CLAMP,
SAMPLE and SAMPLE/PRELOAD. Each instruction defines the set of data register(s)
that may operate and interact with the on-chip system logic while the instruction is
current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the
EXTEST, SAMPLE or SAMPLE/PRELOAD instructions are active. The single-bit
bypass register shift stage is enabled for serial access between TDI and TDO when the
BYPASS, HIGHZ, CLAMP or reserved instructions are active. The functionality of each
test mode is explained in more detail in
48.1.3.3 Bypass mode
When no test operation is required, the BYPASS instruction can be loaded to place the
JTAGC block into bypass mode. While in bypass mode, the single-bit bypass shift
register is used to provide a minimum-length serial path to shift data between TDI and
TDO.
48.2 External signal description
The JTAGC consists of a set of signals that connect to off chip development tools and
allow access to test support functions. The JTAGC signals are outlined in the following
table and described in the following sections.
Name
TCK
TDI
TDO
Output
TMS
1. TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A weak pull may be
implemented at the TDO pad for use when JTAGC is inactive.
Freescale Semiconductor, Inc.
JTAGC block
Table 48-1. JTAG signal properties
I/O
Input
Test Clock
Input
Test Data In
Test Data Out
Input
Test Mode Select
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 48 JTAG Controller (JTAGC)
instructions.
Function
Reset State
Pull
—
Down
—
Up
1
High Z
—
—
Up
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