Module Clocks - NXP Semiconductors freescale KV4 Series Reference Manual

Module clocks

Any bus access to a peripheral that has its clock disabled generates an error termination.
6.5 Module clocks
The following table summarizes the clocks associated with each module.
Module
ARM Cortex-M4 core
NVIC
DAP
ITM
cJTAG, JTAGC
DMA
DMA Mux
Port control
Crossbar Switch
Peripheral bridges
XBARA,XBARB,AOI
LLWU, PMC, SIM, RCM
Mode controller
MCM
EWM
Watchdog timer
MCG
OSC
Flash Controller
Flash memory
nanoedge module
CRC
100
Table 6-1. Module clocks
Bus interface clock
Core modules
Core/System clock
Core/System clock
Core/System clock
Core/System clock
—
System modules
Core/System clock
Bus / Flash clock
Bus / Flash clock
Core/System clock
Core/System clock
Bus / Flash clock
Bus/ Flash clock
Bus / Flash clock
Core/System clock
Bus / Flash clock
Bus / Flash clock
Clocks
Bus /Flash clock MCGOUTCLK, MCGPLLCLK,
Bus / Flash clock
Memory and memory interfaces
Core/System clock
Bus /Flash clock
Fast Peripheral clock +
MCGPLLCLK or
MCGPLL2XCLK
Security
Core/System clock
Analog
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Internal clocks
Core clock
—
—
—
—
—
—
LPO
—
Bus clock, Flash clock
LPO
—
—
LPO
LPO
MCGFLLCLK, MCGIRCLK,
OSCERCLK,
OSCERCLK_UNDIV
OSCERCLK,
OSCERCLK_UNDIV
Flash clock
—
—
—
I/O interface clocks
—
—
—
—
JTAG_CLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor, Inc.