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45.5.4.1.2 SCL high timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T
A HIGH timeout occurs after a START condition appears on the bus but before a STOP
condition appears on the bus. Any master detecting this scenario can assume the bus is
free when either of the following occurs:
• SHTF1 rises.
• The BUSY bit is high and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,
another kind of timeout occurs. The time period must be defined in software. SHTF2 is
used as the flag when the time limit is reached. This flag is also an interrupt resource, so
it triggers IICIF.
45.5.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T
T
. When in master mode, the I2C module must not cumulatively extend its
LOW:MEXT
clock cycles for a period greater than T
defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
Start
SCL
SDA
A master is allowed to abort the transaction in progress to any slave that violates the
T
or T
LOW:SEXT
TIMEOUT,MIN
STOP condition at the conclusion of the byte transfer in progress. When a slave, the I2C
module must not cumulatively extend its clock cycles for a period greater than
T
during any message from the initial START to the STOP. When CSMBCLK
LOW:SEXT
TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF.
Freescale Semiconductor, Inc.
, it assumes that the bus is idle.
HIGH:MAX
LOW:MEXT
T
ClkAck
T
LOW:MEXT
Figure 45-16. Timeout measurement intervals
specifications. To abort the transaction, the master issues a
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 45 Inter-Integrated Circuit (I2C)
within a byte, where each byte is
LOW:SEXT
ClkAck
T
T
LOW:MEXT
LOW:MEXT
and
LOW:SEXT
Stop
1255
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