Cntin Register Update; Mod Register Update; Cnv Register Update - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description

39.5.10.1 CNTIN register update

The following table describes when CNTIN register is updated:
When
CLKS[1:0] = 0:0
• FTMEN = 0, or
• CNTINC = 0
• FTMEN = 1,
• SYNCMODE = 1, and
• CNTINC = 1

39.5.10.2 MOD register update

The following table describes when MOD register is updated:
When
CLKS[1:0] = 0:0
• CLKS[1:0] ≠ 0:0, and
• FTMEN = 0
• CLKS[1:0] ≠ 0:0, and
• FTMEN = 1

39.5.10.3 CnV register update

The following table describes when CnV register is updated:
When
CLKS[1:0] = 0:0
• CLKS[1:0] ≠ 0:0, and
• FTMEN = 0
972
Table 39-244. CNTIN register update
When CNTIN register is written, independent of FTMEN bit.
At the next system clock after CNTIN was written.
By the CNTIN register synchronization.
Table 39-245. MOD register update
When MOD register is written, independent of FTMEN bit.
According to the CPWMS bit, that is:
• If the selected mode is not CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to CNTIN. If
the FTM counter is at free-running counter mode then this update occurs
when the FTM counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to (MOD –
0x0001).
By the MOD register synchronization.
Table 39-246. CnV register update
When CnV register is written, independent of FTMEN bit.
According to the selected mode, that is:
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Then CNTIN register is updated
Then MOD register is updated
Then CnV register is updated
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