Deadtime Insertion - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

Table 39-248. Software ouput control behavior when (COMP = 1)

• The CH(n)OC and CH(n+1)OC bits should be equal.

• The COMP bit must not be modified when software output

control is enabled, that is, CH(n)OC = 1 and/or CH(n

• Software output control has the same behavior with

disabled or enabled FTM counter (see the CLKS field

description in the Status and Control register).

39.5.14 Deadtime insertion

The deadtime insertion is enabled when (DTEN = 1) and (DTVAL[5:0] is non- zero).

DEADTIME register defines the deadtime delay that can be used for all FTM channels.

The DTPS[1:0] bits define the prescaler for the system clock and the DTVAL[5:0] bits

define the deadtime modulo, that is, the number of the deadtime prescaler clocks.

The deadtime delay insertion ensures that no two complementary signals (channels (n)

and (n+1)) drive the active state at the same time.

If POL(n) = 0, POL(n+1) = 0, and the deadtime is enabled, then when the channel (n)

match (FTM counter = C(n)V) occurs, the channel (n) output remains at the low value

until the end of the deadtime delay when the channel (n) output is set. Similarly, when the

channel (n+1) match (FTM counter = C(n+1)V) occurs, the channel (n+1) output remains

at the low value until the end of the deadtime delay when the channel (n+1) output is set.

See the following figures.

If POL(n) = 1, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n)

match (FTM counter = C(n)V) occurs, the channel (n) output remains at the high value

until the end of the deadtime delay when the channel (n) output is cleared. Similarly,

KV4x Reference Manual, Rev. 2, 02/2015

Channel (n) Output

is not modified by SWOC

is forced to zero

is forced to one

Channel (n+1) Output

is not modified by SWOC

is forced to zero

is forced to one

is forced to zero

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