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30.1.2 Modes of Operation
The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI,
BLPE, and Stop. For details, see
30.2 External Signal Description
There are no MCG signals that connect off chip.
30.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The MCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus error. Read accesses may be performed in both supervisor
and user mode.
Absolute
address
(hex)
4006_4000
MCG Control 1 Register (MCG_C1)
4006_4001
MCG Control 2 Register (MCG_C2)
4006_4002
MCG Control 3 Register (MCG_C3)
4006_4003
MCG Control 4 Register (MCG_C4)
4006_4004
MCG Control 5 Register (MCG_C5)
4006_4005
MCG Control 6 Register (MCG_C6)
4006_4006
MCG Status Register (MCG_S)
4006_4008
MCG Status and Control Register (MCG_SC)
MCG Auto Trim Compare Value High Register
4006_400A
(MCG_ATCVH)
MCG Auto Trim Compare Value Low Register
4006_400B
(MCG_ATCVL)
4006_400D MCG Control 8 Register (MCG_C8)
Freescale Semiconductor, Inc.
MCG modes of
MCG memory map
Register name
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 30 Multipurpose Clock Generator (MCG)
operation.
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R
8
R/W
8
R/W
8
R/W
8
R/W
Section/
Reset value
page
04h
30.3.1/550
80h
30.3.2/551
Undefined
30.3.3/552
Undefined
30.3.4/553
00h
30.3.5/554
00h
30.3.6/555
10h
30.3.7/557
02h
30.3.8/558
00h
30.3.9/560
30.3.10/
00h
560
30.3.11/
80h
560
549
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