Flexcan Signal Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

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This low-power mode is entered when the MDIS bit in the MCR Register is asserted

by the CPU and the LPM_ACK is asserted by the FlexCAN. When disabled, the

module requests to disable the clocks to the CAN Protocol Engine and Controller

Host Interface submodules. Exit from this mode is done by negating the MDIS bit in

the MCR register. See

• Doze mode:

This low power mode is entered when the DOZE bit in MCR is asserted and Doze

mode is requested at MCU level and the LPM_ACK bit in the MCR Register is

asserted by the FlexCAN. When in Doze mode, the module requests to disable the

clocks to the CAN Protocol Engine and the CAN Controller-Host Interface sub-

modules. Exit from this mode happens when the DOZE bit in MCR is negated, when

the MCU is removed from Doze mode, or when activity is detected on the CAN bus

and the Self Wake Up mechanism is enabled. See

• Stop mode:

This low power mode is entered when Stop mode is requested at MCU level and the

LPM_ACK bit in the MCR Register is asserted by the FlexCAN. When in Stop

Mode, the module puts itself in an inactive state and then informs the CPU that the

clocks can be shut down globally. Exit from this mode happens when the Stop mode

request is removed, or when activity is detected on the CAN bus and the Self Wake

Up mechanism is enabled. See

43.3 FlexCAN signal descriptions

The FlexCAN module has two I/O signals connected to the external MCU pins. These

signals are summarized in the following table and described in more detail in the next

subsections.

CAN Receive Pin

CAN Transmit Pin

43.3.1 CAN Rx

This pin is the receive pin from the CAN bus transceiver. Dominant state is represented

by logic level 0. Recessive state is represented by logic level 1.

Freescale Semiconductor, Inc.

Module Disable mode

Table 43-1. FlexCAN signal descriptions

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 43 Flex Controller Area Network (FlexCAN)

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