Block Parts - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
eDMA system
eDMA e ngine
Read Data
Data Path
Write Data
Address

23.1.2 Block parts

The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer-control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Submodule
Address path This block implements registered versions of two channel transfer control descriptors, channel x
and channel y, and manages all master bus-address calculations. All the channels provide the
same functionality. This structure allows data transfers associated with one channel to be
preempted after the completion of a read/write sequence if a higher priority channel activation is
asserted while the first channel is active. After a channel is activated, it runs until the minor loop is
completed, unless preempted by a higher priority channel. This provides a mechanism (enabled
by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time
another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local memory and
loaded into the address path channel x registers for a normal start and into channel y registers for
a preemption start. After the minor loop completes execution, the address path hardware writes
368
Address Path
Figure 23-1. eDMA system block diagram
Table 23-1. eDMA engine submodules
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Transfer Control
Descriptor (TCD)
64
Program Model/
Channel Arbitration
Control
eDMA Peripheral
eDMA Done
Request
Function
Freescale Semiconductor, Inc.
Write Address
Write Data
0
1
2
n-1
Read Data