Block Diagram - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
40.2 Introduction
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA
channels.

40.2.1 Block diagram

The following figure shows the block diagram of the PIT module.
Peripheral bus
Interrupts
Triggers
Peripheral
bus clock
See the chip-specific PIT information for the number of PIT
channels used in this MCU.
40.2.2 Features
The main features of this block are:
• Ability of timers to generate DMA trigger pulses
1028
PIT
PIT
registers
Figure 40-1. Block diagram of the PIT
NOTE
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
load_value
Timer 1
Timer n
Freescale Semiconductor, Inc.