Run Modes - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

16.4.2.3 Aborted stop mode entry

If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the

transition early and return to RUN mode without completely entering the stop mode. An

aborted entry is possible only if the reset or interrupt occurs before the PMC begins the

transition to stop mode regulation. After this point, the interrupt or reset is ignored until

the PMC has completed its transition to stop mode regulation. When an aborted stop

mode entry sequence occurs, SMC_PMCTRL[STOPA] is set to 1.

16.4.2.4 Transition to wait modes

For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking

continues, as in RUN and VLPR mode operation. Some modules that support stop-in-

wait functionality have their clocks disabled in these configurations.

16.4.2.5 Transition from stop modes to Debug mode

The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back

to a Halted state when the debugger has been enabled. As part of this transition, system

clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking

configuration.

16.4.3 Run modes

The run modes supported by this device can be found here.

• Very Low-Power Run (VLPR)

• High Speed Run (HSRUN)

16.4.3.1 RUN mode

This is the normal operating mode for the device.

This mode is selected after any reset. When the ARM processor exits reset, it sets up the

stack, program counter (PC), and link register (LR):

• The processor reads the start SP (SP_main) from vector-table offset 0x000

• The processor reads the start PC from vector-table offset 0x004

• LR is set to 0xFFFF_FFFF.

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 16 System Mode Controller (SMC)