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Chapter 46
Universal Asynchronous Receiver/Transmitter
(UART) / FlexSCI
46.1
Chip-specific UART information
46.1.1 UART configuration information
This chip contains two UART modules. This section describes how each module is
configured on this device.
1. Standard features of all UARTs:
• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data
2. UART0 and UART1 are clocked from the fast bus clock. The maximum baud rate is
1/16 of related source clock frequency.
3. UART0 contains 8-entry transmit and 8-entry receive FIFOs
4. All other UARTs contain a 1-entry transmit and receive FIFOs
46.1.2 UART signals
Signal
Receive complete
Output
Transmit complete
Output
UART0RXSRC
Input
UART0TXSRC
Input
Receive complete
Output
Freescale Semiconductor, Inc.
I/O
UART0
DMA_MUX source 2
DMA_MUX source 3
UART0_RXpin or CMP0_OUT or CMP1_OUT
UART0_TX pin or UART0_TX pin modulated with FTM1 channel 0 output
UART1
DMA_MUX source 4
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Connected to
1265
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