Addressing Modes - Freescale Semiconductor MC9S08PT60 Reference Manual

Table 10-1. CCR Register Field Descriptions (continued)
Field Description
1 Interrupts disabled
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or
2
data manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an
N
8-bit or 16-bit value causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data
1
manipulation produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value
Z
causes Z to be set if the loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
0 Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a
carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some
C
instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7

10.3 Addressing Modes

Addressing modes define the way the CPU accesses operands and data. In the HCS08
V6, memory, status and control registers, and input/output (I/O) ports share a single 64
KB CPU address space. This arrangement means that the same instructions that access
variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions
use one addressing mode to specify the source operand and a second addressing mode to
specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and DBNZ
use one addressing mode to specify the location of an operand for a test and then use
relative addressing mode to specify the branch destination address when the tested
condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested,
and relative addressing mode is implied for the branch destination.
Every addressing mode, except inherent, generates a 16-bit effective address. The
effective address is the address of the memory location that the instruction acts on.
Effective address computations do not require extra execution cycles. The HCS08 V6
CPU uses the 16 addressing modes described in the following sections.
Freescale Semiconductor, Inc.
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Chapter 10 Central processor unit
267