ST STM32L4+ Series Reference Manual page 1834

Low-power universal asynchronous receiver transmitter (LPUART)
51.6 LPUART registers
Refer to
The peripheral registers have to be accessed by words (32 bits).
51.6.1 LPUART control register 1 [alternate] (LPUART_CR1)
Address offset: 0x00
Reset value: 0x0000 0000
The same register can be used in FIFO mode enabled (this section) and FIFO mode
disabled (next section).
FIFO mode enabled
31 30 29
RXF FIFO
TXFEIE
FIE EN
rw rw rw
15 14 13
Res. CMIE MME
rw rw
Bit 31 RXFFIE:RXFIFO Full interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when RXFF=1 in the LPUART_ISR register
Bit 30 TXFEIE:TXFIFO empty interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated when TXFE=1 in the LPUART_ISR register
Bit 29 FIFOEN:FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = '00': 1 Start bit, 8 Data bits, n Stop bit
M[1:0] = '01': 1 Start bit, 9 Data bits, n Stop bit
M[1:0] = '10': 1 Start bit, 7 Data bits, n Stop bit
This bit can only be written when the LPUART is disabled (UE=0).
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate
Bits 27:26 Reserved, must be kept at reset value.
1834/2301
Section 1.2 on page 84
28 27 26 25
M1 Res. Res.
rw rw
12 11 10 9
M0 WAKE PCE PS
rw rw rw rw
(0x7F and 0x55 frames detection) are not supported.
for a list of abbreviations used in register descriptions.
24 23 22
DEAT[4:0]
rw rw rw
8 7 6
TXFN RXFN
PEIE TCIE
FIE
rw rw rw
RM0432 Rev 6
21 20 19 18
DEDT[4:0]
rw rw rw rw
5 4 3 2
IDLEIE TE RE
EIE
rw rw rw rw
RM0432
17 16
rw rw
1 0
UESM UE
rw rw