ST STM32L4+ Series Reference Manual page 1823

RM0432
In this example, the current address of the receiver is 1
(programmed in the LUART_CR2 register)
RX
RWU
51.4.10 LPUART parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the LPUART_CR1 register. Depending on the frame
length defined by the M bits, the possible LPUART frame formats are as listed in
M bits
00
00
01
01
10
10
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
2. In the data register, the PB is always taking the MSB position (8th or 7th, depending on the M bit value).
Even parity
The parity bit is calculated to obtain an even number of "1s" inside the frame which is made
of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit is equal to 0 if even
parity is selected (PS bit in LPUART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 6, 7
or 8 LSB bits (depending on M bit values) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit is equal to 1 if odd parity
is selected (PS bit in LPUART_CR1 = 1).
Low-power universal asynchronous receiver transmitter (LPUART)
Figure 522. Mute mode using address mark detection
IDLE Addr=0 Data 1 Data 2
MMRQ written to 1
(RXNE was cleared)
Non-matching address
Table 362: LPUART frame formats
PCE bit
0
1
0
1
0
1
IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5
Mute mode
Matching address
| SB | 7-bit data | PB | STB |
| SB | 8-bit data PB | STB |
| SB | 6-bit data | PB | STB |
RM0432 Rev 6
RXNE RXNE RXNE
Normal mode
Non-matching address
(1)
LPUART frame
| SB | 8 bit data | STB |
| SB | 9-bit data | STB |
| SB | 7bit data | STB |
Mute mode
MSv31888V1
Table 362.
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