Full Duplex Single Transfer Format With Pha = 1; Master Mode - Texas Instruments CC3200 Technical Reference Manual

Functional Description
Figure 8-4. Full Duplex Single Transfer Format with PHA = 1
t — Minimum leading time required for slave mode (guaranteed in master mode) before the first
Lead
SPICLK edge.
t — Minimum trailing time required for slave mode (guaranteed in master mode) after the last SPICLK
Lag
edge.
In 3-pin mode without using the SPIEN signal, the controller provides the same waveform, with SPIEN
forced to low state. In 3-pin slave mode, SPIEN is useless.

8.2.3 Master Mode

SPI is in master mode when the MS bit of the SPI_MODULCTRL register is cleared.
8.2.3.1 Interrupt Events in Master Mode
In master mode, the interrupt events related to the transmitter register state are TX_empty and
TX_underflow. The interrupt event related to the receiver register state is RX_full.
8.2.3.1.1 TX_empty
The event TX_empty is activated when a channel is enabled and its transmitter register becomes empty
(transient event). Enabling the channel automatically raises this event. When the FIFO buffer is enabled
(MCSPI_CHCONF[FFEW] set to 1), the TX_empty is asserted once there is enough space in buffer to
write the number of bytes defined by MCSPI_XFERLEVEL[AEL].
The transmitter register must be loaded to remove the source of the interrupt, and the TX_empty interrupt
status bit must be cleared for interrupt line de-assertion (if the event is enabled as an interrupt source).
When FIFO is enabled, no new TX_empty event is asserted when the local host has not performed the
number of writes into the transmitter register, defined by MCSPI_XFERLEVEL[AEL]. The local host must
perform the correct number of writes.
250
SPI (Serial Peripheral Interface)
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SWRU367D – June 2014 – Revised May 2018
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