ST STM32F40 Series Reference Manual page 1090

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RM0090
OTG_FS device V
Address offset: 0x082C
Reset value: 0x0000 05B8
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP: Device V
Specifies the V
OTG_FS device IN endpoint FIFO empty interrupt mask register:
(OTG_FS_DIEPEMPMSK)
Address offset: 0x834
Reset value: 0x0000 0000
This register is used to control the IN endpoint FIFO empty interrupt generation
(TXFE_OTG_FS_DIEPINTx).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
pulsing time register (OTG_FS_DVBUSPULSE)
BUS
BUS
Reserved
pulsing time
BUS
pulsing time during SRP. This value equals:
BUS
V
pulsing time in PHY clocks / 1 024
BUS
Reserved
These bits act as mask bits for OTG_FS_DIEPINTx.
TXFE interrupt one bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3
0: Masked interrupt
1: Unmasked interrupt
Doc ID 018909 Rev 4
USB on-the-go full-speed (OTG_FS)
pulsing time during SRP.
rw rw rw rw rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
9
8
7
6
5
4
3
DVBUSP
9
8
7
6
5
4
3
INEPTXFEM
2
1
0
2
1
0
1090/1422

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