ST STM32F40 Series Reference Manual page 1091

USB on-the-go full-speed (OTG_FS)
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
Address offset: 0x900
Reset value: 0x0000 0000
This section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use
registers for endpoints 1–3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r w w rw rw rw rw
Bit 31 EPENA: Endpoint enable
– Endpoint disabled
– Transfer completed
Bit 30 EPDIS: Endpoint disable
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 SNAK: Set NAK
Bit 26 CNAK: Clear NAK
A write to this bit clears the NAK bit for the endpoint.
Bits 25:22 TXFNUM: TxFIFO number
Bit 21 STALL: STALL handshake
Bit 20 Reserved, must be kept at reset value.
Bits 19:18 EPTYP: Endpoint type
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TXFNUM EPTYP
rs r
The application sets this bit to start transmitting data on the endpoint 0.
The core clears this bit before setting any of the following interrupts on this endpoint:
The application sets this bit to stop transmitting data on an endpoint, even before the
transfer for that endpoint is complete. The application must wait for the Endpoint disabled
interrupt before treating the endpoint as disabled. The core clears this bit before setting the
Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is
already set for this endpoint.
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the transmission of NAK handshakes on an
endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on
that endpoint.
This value is set to the FIFO number that is assigned to IN endpoint 0.
The application can only set this bit, and the core clears it when a SETUP token is received
for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit,
the STALL bit takes priority.
Hardcoded to '00' for control.
Doc ID 018909 Rev 4
r r r
9 8 7 6 5 4 3
Reserved
RM0090
2 1 0
MPSIZ
rw rw