Dma Operation Register (Dmaor) - Hitachi SH7709S Hardware Manual

11.2.5

DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 16-bit readable/writable register that controls the
DMAC transfer mode.
These register values are initialized to 0 in a reset. The previous value is retained in standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: * Only 0 can be written to the AE and NMIF bits after 1 is read.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 9 and 8—Priority Mode Bits 1 and 0 (PR1, PR0): Select the priority level between
channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1 Bit 8: PR0
0 0
0 1
1 0
1 1
Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
15 14 13
— — —
0 0 0
R R R
7 6 5
— — —
0 0 0
R R R
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round-robin
12 11 10
— — —
0 0 0
R R R
4 3 2
— — AE
0 0 0
R R R/(W)*
9 8
PR1 PR0
0 0
R/W R/W
1 0
NMIF DME
0 0
R/(W)* R/W
(Initial value)
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