Dma Operation Register (Dmaor) - Hitachi SH7095 Hardware User Manual

9.2.7

DMA Operation Register (DMAOR)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Note: The only writing permitted is 0 to clear the flag.
The DMA operation register (DMAOR) is a 32-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. Only the bottom four of the 32 bits are
effective. DMAOR is written as a 32-bit value, including the top 28 bits. Write the initial values to
the top 28 bits. They always read 0. DMAOR is initialized to H'00000000 by a reset or the standby
mode.
• Bits 31–4—Reserved: These bits cannot be modified. They always read 0.
• Bit 3—Priority Mode Bit (PR): Selects the priority level between channels when there are
transfer requests for multiple channels. It is initialized to 0 by a reset and in the standby mode.
Values are held during a module standby.
Bit 3: PR
0
1
• Bit 2—Address Error Flag Bit (AE): This flag indicates that an address error has occurred in
the DMAC. When the AE bit is set to 1, the DMA transfer cannot be enabled even if the DE
bit in the DMA channel control register (CHCR) is set to 1. To clear the AE bit, read 1 from it
and then write 0 carried out in the DMAC transfer being executed when the address error
arose. AE is initialized to 0 by a reset or in the standby mode.
31 30 29
— — —
0 0
R R
7 6
— — —
0 0
R R
Description
Fixed priority (Ch 0 > Ch 1) (initial value)
Round-robin (Top priority shifts to bottom after each transfer . The
priority for the first DMA transfer after a reset is Ch 1 > Ch 0)
... 11
... —
0 ... 0
R ... R
5 4 3
— PR
0 0 0
R R R/W
10 9
— —
0 0
R R
2 1
AE NMIF
0 0
R/(W)* R/(W)*
Hitachi 233
8
—
0
R
0
DMIE
0
R/W