Dmac Multi-Channel Operation; Figure 7.21 Example Of Dreq Level Activated Block Transfer Mode Transfer - Hitachi H8S/2215 Series Hardware Manual

Bus release
Address bus
DMA control
Channel
Minimum of 2 cycles
[1]
[1] Acceptance after transfer enabling; the
edge of , and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the
is held.)
Figure 7.21 Example of DREQ
DREQ signal sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ signal low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. Acceptance resumes after the end of the dead cycle, DREQ signal low level
sampling is performed again, and this operation is repeated until the transfer ends.
Note : The DREQ signal of this chip is an internal signal of chip, so it is not output from the pin.
7.4.10

DMAC Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9
summarizes the priority order for DMAC channels.
Rev. 3.0, 10/02, page 186 of 686
1 block transfer
DMA
read
Transfer
source
Idle Read Write
Request clear period
Request
[2] [3]
signal low level is sampled on the rising edge of , and the request
DREQ Level Activated Block Transfer Mode Transfer
DREQ DREQ
DMA
Bus DMA
DMA
release
dead
write
read
Transfer Transfer
destination source
Dead Idle Read
Request clear period
Request
Minimum of 2 cycles
[4] [5] [6]
Acceptance resumes
signal low level is sampled on the rising
1 block transfer
DMA
write
Transfer
destination
Write Dead
[7]
Acceptance resumes
Bus
release
Idle