Input Sampling And A/D Conversion Time - Hitachi H8/3672 Series Hardware Manual

14.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
starts conversion. Figure 14-2 shows the A/D conversion timing. Table 14-3 shows the A/D
conversion time.
As indicated in figure 14-2, the A/D conversion time includes t
length of t varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 14-3.
In scan mode, the values given in table 14-3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
Address
Write signal
Input sampling
timing
ADF
Rev. 1.0, 03/01, page 200 of 280
(1)
ø
(2)
t
D
Legend
(1) : ADCSR write cycle
(2) : ADCSR address
t : A/D conversion start delay
D
t : Input sampling time
SPL
t : A/D conversion time
CONV
Figure 14-2 A/D Conversion Timing
) has passed after the ADST bit is set to 1, then
D
and the input sampling time. The
D
t
SPL
t
CONV