Input Sampling And A/D Conversion Time - Hitachi H8/3032 Series Hardware Manual

Table of Contents

Advertisement

Downloaded from
Elcodis.com
electronic components distributor

12.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
after the ADST bit is set to 1, then starts conversion. Figure 12-5 shows the A/D
D
conversion timing. Table 12-4 indicates the A/D conversion time.
As indicated in figure 12-5, the A/D conversion time includes t
length of t
varies depending on the timing of the write access to ADCSR. The total conversion
D
time therefore varies within the ranges indicated in table 12-4.
In scan mode, the values given in table 12-4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
ø
Address bus
(2)
Write signal
Input sampling
timing
ADF
t
D
Legend
(1):
ADCSR write cycle
(2):
ADCSR address
t :
Synchronization delay
D
t
:
Input sampling time
SPL
t
:
A/D conversion time
CONV
Figure 12-5 A/D Conversion Timing
and the input sampling time. The
D
t
SPL
t
CONV
385

Advertisement

Table of Contents
loading

Table of Contents