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17.4.3
Input Sampling and A/D Conversion Time
The A/D converter includes the sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
then conversion is started. Figure 17.2 shows the A/D conversion timing. Table 17.3 shows the
A/D conversion time.
As shown in figure 17.2, the A/D conversion time (t
The length of t
varies depending on the timing of the write access to ADCSR. Therefore, the total
D
conversion time varies within the range shown in table 17.3.
In scan mode, the values given in table 17.3 indicate the first conversion time. The second and
subsequent conversion time is shown in table 17.4. In both cases, set bits CKS1 and CKS0 in
ADCR within the range shown in table 23.7 in section 23, Electrical Characteristics.
φ
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
(2)
t
D
t
SPL
t
CONV
(1)
(2)
t
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
Figure 17.2 A/D Conversion Timing
) has passed after the ADST bit is set to 1, and
D
) includes t
CONV
t
SPL
t
CONV
and input sampling time (t
D
Rev. 1.0, 09/02, page 435 of 568
).
SPL
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