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9.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time t
after the ADST bit is set to "1." The sampling process lasts for a time t
D
conversion begins after sampling is completed. Figure 9-4 shows the timing of these steps.
Table 9-4 (a) lists the conversion times for the single mode. Table 9-4 (b) lists the conversion times
for the scan mode.
The total conversion time (t
ADCSR write time with the A/D conversion process, so the length of t
conversion time therefore varies within the minimum to maximum ranges indicated in table 9-4 (a)
and (b).
In the scan mode, the ranges given in table 9-4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = "0") or 128 states
(when CKS = "1").
Ø
Internal address bus
Write signal
Input sampling timing
ADF
(1):
ADCSR write cycle
(2):
ADCSR address
t
:
Synchronization delay
D
t
:
Input sampling time
SPL
t
:
Total A/D conversion time
CONV
) includes t
and t
CONV
D
(1)
(2)
t
D
Figure 9-4. A/D Conversion Timing
222
. The purpose of t
SPL
D
is variable. The total
D
t
SPL
t
CONV
. The actual A/D
SPL
is to synchronize the
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