Sci Interrupt Sources And The Dmac; Notes On Use - Hitachi SH7095 Hardware User Manual

13.4

SCI Interrupt Sources and the DMAC

The SCI has four interrupt sources in each channel. transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.13 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in the SSR is set to 1. TXI can start the direct memory access
controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes
data in the transmit data register (TDR).
RXI is requested when the RDRF bit in the SSR is set to 1. RXI can start the DMAC to transfer
data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR).
ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the
DMAC.
TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC. Where the
TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the
transmit operation is complete.
Table 13.13 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
See section 4, Exception Processing, for information on the priority order and relationship to non-
SCI interrupts.
13.5

Notes on Use

Note the following points when using the SCI.
TDR Write and TDRE Flags: The TDRE bit in the serial status register (SSR) is a status flag
indicating loading of transmit data from the TDR into the TSR. The SCI sets TDRE to 1 when it
transfers data from the TDR to the TSR. Data can be written to the TDR regardless of the TDRE
bit status. If new data is written in the TDR when TDRE is 0, however, the old data stored in the
TDR will be lost because the data has not yet been transferred to the TSR. Before writing transmit
data to the TDR, be sure to check that TDRE is set to 1.
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
DMAC Availability
No
Yes
Yes
No
Priority
High
↑
↓
Low
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