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3.4
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ15 to IRQ0) and internal interrupts
(56 sources).
3.4.1
External Interrupts
There are 17 external interrupt sources: NMI and IRQ15 to IRQ0. Setting an SSI bit to 1 in SSIER
enables the corresponding IRQ15–IRQ0 interrupt to be used as a software standby mode release
source.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The
NMIEG bit in INTCR specifies whether an interrupt is requested at a rising edge or a falling edge
on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins
IRQ15 to IRQ0. Interrupts IRQ15 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ15 to IRQ0.
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
0 by software.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 3.2.
IRQnSCA, IRQnSCB
IRQn
input
Note: n = 15 to 0
Figure 3.2 Block Diagram of Interrupts IRQ15 to IRQ0
66
Edge/
level detection
circuit
Clear signal
IRQnE
IRQnF
S
Q
R
IRQn interrupt
request
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