Next Data Register B (Ndrb) - Hitachi H8/3032 Series Hardware Manual

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9.2.6 Next Data Register B (NDRB)

NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP to TP ). During TPC output, when an ITU compare match event specified in
15 8
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3
and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA4
Bit 7
NDR15 NDR14
Initial value 0
Read/Write R/W R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Address H'FFA6
Bit 7
—
Initial value 1
Read/Write —
6 5 4 3
NDR13 NDR12 NDR11
0 0 0 0
R/W R/W R/W
6 5 4 3
— — — —
1 1 1 1
— — — —
Reserved bits
277
2 1 0
NDR10 NDR9 NDR8
0 0 0
R/W R/W R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
2 1 0
— — —
1 1 1
— — —