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10.2.6
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP
to TP
15
specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The
address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output
trigger or different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by
the same compare match event, the NDRB address is H'FFFA4. The upper 4 bits belong to group
3 and the lower 4 bits to group 2. Address H'FFFA6 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA4
Bit
NDR15
Initial value
Read/Write
R/W
Address H'FFFA6
Bit
Initial value
Read/Write
). During TPC output, when an 16-bit timer compare match event
8
7
6
NDR14
NDR13
0
0
R/W
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
7
6
—
—
1
1
—
—
5
4
NDR12
NDR11
0
0
R/W
R/W
5
4
—
—
1
1
—
—
Reserved bits
3
2
NDR10
NDR9
0
0
R/W
R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
3
2
—
—
1
1
—
—
1
0
NDR8
0
0
R/W
1
0
—
—
1
1
—
—
281
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