Interrupt Sources And Dma Controller Activation - Hitachi H8/3006 Hardware Manual

9.5.3

Interrupt Sources and DMA Controller Activation

Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare
match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources
of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag
are set to 1.
The priority order of the channels can be modified in interrupt priority register A (IPRA). For
details see section 5, Interrupt Controller.
Compare match/input capture A interrupts in channels 0 to 2 can activate the DMA controller
(DMAC). When the DMAC is activated a CPU interrupt is not requested.
Table 9.6 lists the interrupt sources.
Table 9.6 16-bit timer Interrupt Sources
Interrupt
Channel Source
0 IMIA0
IMIB0
OVI0
1 IMIA1
IMIB1
OVI1
2 IMIA2
IMIB2
OVI2
Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed
by settings in IPRA.
334
Description
Compare match/input capture A0
Compare match/input capture B0
Overflow 0
Compare match/input capture A1
Compare match/input capture B1
Overflow 1
Compare match/input capture A2
Compare match/input capture B2
Overflow 2
DMAC
Activatable Priority*
Yes High
No
No
Yes
No
No
Yes
No
No Low