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6.5.2
Pin States in Idle Cycle
Table 6.5 shows the pin states in an idle cycle.
Table 6.5
Pin States in Idle Cycle
Pins
A
to A
23
0
D
to D
15
0
CSn
AS
RD
HWR
LWR
6.6
Bus Arbiter
The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus
master can be either the CPU or an external bus master. When a bus master has the bus right it can
carry out read and write operations. Each bus master uses a bus request signal to request the bus
right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to
grant the bus to a bus master, which can the operate using the bus.
The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and
returns an acknowledge signal to the bus master. When two or more bus masters request the bus,
the highest-priority bus master receives an acknowledge signal. The bus master that receives an
acknowledge signal can continue to use the bus until the acknowledge signal is deactivated.
The bus master priority order is:
(High)
External bus master > CPU
The bus arbiter samples the bus request signals and determines priority at all times, but it does not
always grant the bus immediately, even when it receives a bus request from a bus master with
higher priority than the current bus master. Each bus master has certain times at which it can
release the bus to a higher-priority bus master.
Pin State
Next cycle address value
High impedance
High
High
High
High
High
(Low)
133
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