Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1) - ST STM32F446 Series Reference Manual

Advanced-control timers (TIM1&TIM8)
16.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13
OC2
OC2M[2:0]
CE
IC2F[3:0]
rw rw rw
Output compare mode:
Bit 15 OC2CE: Output Compare 2 clear enable
Bits 14:12 OC2M[2:0]: Output Compare 2 mode
Bit 11 OC2PE: Output Compare 2 preload enable
Bit 10 OC2FE: Output Compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input
504/1328
12 11 10 9
OC2 OC2
PE FE
CC2S[1:0]
IC2PSC[1:0]
rw rw rw rw
8 7 6
OC1
OC1M[2:0]
CE
IC1F[3:0]
rw rw rw
RM0390 Rev 4
5 4 3 2
OC1 OC1
PE FE
IC1PSC[1:0]
rw rw rw rw
RM0390
1 0
CC1S[1:0]
rw rw