Module Standby Control Register L (Mstcrl) - Hitachi H8/3006 Hardware Manual

Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1 Description
0 SCI1 operates normally
1 SCI1 is in standby state
Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0
MSTPH0 Description
0 SCI0 operates normally
1 SCI0 is in standby state
19.2.3

Module Standby Control Register L (MSTCRL)

MSTCRL is an 8-bit readable/writable register that controls the module standby function, which
places individual on-chip supporting modules in the standby state. Module standby can be
designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules.
Bit
MSTPL7
Initial value
Read/Write R/W
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby.
Bit 7
MSTPL7 Description
0 DMAC operates normally
1 DMAC is in standby state
562
7 6 5
— MSTPL5
0 0 0
R/W
R/W
Reserved bits
4 3
MSTPL4 MSTPL3 MSTPL2
0 0
R/W R/W
Module standby L7, L5 to L2, L0
These bits select modules to be
placed in standby
(Initial value)
(Initial value)
2 1
— MSTPL0
0 0
R/W R/W
R/W
(Initial value)
0
0